1. Field of the Invention
The present invention relates to a digital signal time-division multiplex apparatus for time-divisionally multiplexing digital signals transmitted through a plurality of channels.
2. Description of the Related Art
A digital signal time-division multiplex apparatus generally comprises a low-order section frame processor, a high-order section frame processor, and a sync signal generator. As a preliminary treatment of time-division multiplexing, the low-order section frame processor converts digital signals input transmitted through a plurality of channels into low-order section frame signals which are synchronized with one another. The high-order section frame processor receives the low-order section frame signals and selectively outputs the signals within a one-frame period, thereby time-divisionally multiplexing the signals to generate high-order section frame signals. The sync signal generator generates sync signals such as clocks and tuning pulses necessary for a frame converting operation of the low-order section frame processor and a switching operation of a time-division multiplex processor.
The high-order section frame processor and the sync signal generator are each formed of a single electronic circuit board because their processing functions are simple. The low-order section frame processor necessitates a complicated function such as code conversion, frame processing, and buffering. If all the channels are formed in a single electronic circuit board, a mounting area of the board becomes too large. Further, the channels have to be extended. One electronic circuit board is therefore provided for each of the channels.
Since, however, the high-order section frame processor processes a signal of remarkably high frequency, it is arranged away from the low-order section frame processor so as not to exert an adverse influence, such as undesirable radiation, upon the low-order section frame processor.
FIG. 1 shows the structure of a conventional digital signal time-division multiplex apparatus for eight channels, and FIG. 2 is a block diagram showing the conventional apparatus. The blocks of FIG. 2 correspond to the circuit boards of FIG. 1.
In FIGS. 1 and 2, reference numerals 1a to 1h indicate boards each constituting a low-order section frame processor, 2 denotes a board constituting a sync signal generator, and 3 represents a board constituting a high-order section frame processor.
The sync signal generating board 2 receives system clocks SCK to synchronize the board 2 with an external device. In response to the system clocks, the board 2 generates frame sync signals (including clocks), which are to be supplied to the low-order section frame processing boards 1a to 1h, and switching control signals (including clocks) which are to be supplied to the high-order section frame processing board 3. The frame sync signals are transmitted to the boards 1a to 1h through cables 4a to 4h, and the switching control signals are transmitted to the board 3 through a cable 5.
The low-order section frame processing boards 1a to 1h receive digital signals S.sub.IN1 to S.sub.IN8 from channels 1CH to 8CH, respectively, and convert the digital signals into low-order section frame signals in response to the frame sync signals transmitted through the cables 4a to 4h. The low-order section frame signals are transmitted to the high-order section frame processing board 3 through cables 6a to 6h.
The board 3 receives the low-order section frame signals from the cables 6a to 6h and selectively outputs the signals in predetermined order in response to the switching control signals transmitted through the cable 5, thereby time-divisionally multiplexing the signals to generate a high-order section frame signal S.sub.OUT. The high-order section frame signal S.sub.OUT is transmitted to, for example, a transmitter.
A high-speed transmission of digital signals has recently been attained in accordance with progress in digital signal processing technology and in communication technology. Accordingly, high-speed processing is required in the digital signal time-division multiplex apparatus.
To achieve the high-speed processing, however, a difference in length between signal transmission paths in the channels has to be prevented from affecting a phase difference between channel signals. Unless the phases of the low-order section frame signals of all the channels are the same at input terminals, the high-order section frame processing board 3 cannot fulfill a normal successive selecting function.
As described above, in the conventional digital signal time-division multiplex apparatus, the cables 4a to 4h connecting the sync signal generating board 2 and the low-order section frame processing boards 1a to 1h are set to have the same length, so that the phases of the frame sync signals are equalized at the input terminals of the boards 1a to 1h, and the processings of the boards 1a to 1h are synchronized with one another, thereby outputting the low-order section frame signals in the same phase. Further, the cables 6a to 6h connecting the boards 1a to 1h and the board 3 are set to have the same length so that the low-order section frame signals output from the boards 1a to 1h in the same phase are supplied to the base 3 in the same timing.
In the above method for adjusting the phases, the lengths of the cables 4a to 4h and those of the cables 6a to 6h have to be adjusted to the longest cables, respectively, and then the cables have to be formed while adjusting the residual length of each cable. For this reason, a handling operation of these cables is very complicated. The more the channels and the higher the signal transmission speed, the more complicated the handling operation. The reliability of the apparatus is therefore deteriorated.